An Efficient Lifting Scheme Architecture for 2d Discrete Wavelet Transform

A high-speed and reduced-area lifting architecture for 2D Discrete Wavelet Transform computation and the 2-D DWT Image Decomposition is proposed in this work. Lift scheme is one of the wavelet computation techniques. Prior DWT architectures are mostly constructed on the basic lifting scheme or the flipping structure. In order to attain a critical path with only one multiplier, at least four pipelining stages are mandatory for one lifting step, or a large temporal buffer is required. In this work, modifications are made in the lifting scheme as the Radix-8 booth multiplier is used and the intermediate values are recombined and stored to reduce the number of pipelining stages and the registers. The twoinput/two-output parallel scanning architecture is adopted in the design. The detailed analysis is performed to compare the proposed architecture with the modified architecture in terms of hardware complexity computation time and Power consumption. In the proposed architecture, the number of LUTs reduced to 50%, power consumption is reduced to 89mw, and computation time delay is reduced to 36.6% when compared to the conventional Lifting Scheme.